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     See also: Scaling (ss) Field, Index Field, Mode (mod) Field,
               Register/Memory (r/m) Field
 
     In scaled indexing, the base register (base) field combines with
     the mod field to specify the base register and the displacement.
     Scaled addressing is allowed only under the .386 and .486
     directives.
 
     Fields for 32-bit indexed operands are:
 
     mod    r/m     base    Operand
 
     00     100     000     DS:[EAX+(scale*index)]
     00     100     001     DS:[ECX+(scale*index)]
     00     100     010     DS:[EDX+(scale*index)]
     00     100     011     DS:[EBX+(scale*index)]
     00     100     100     SS:[ESP+(scale*index)]
     00     100     101     DS:[disp32+(scale*index)]
     00     100     110     DS:[ESI+(scale*index)]
     00     100     111     DS:[EDI+(scale*index)]
 
     01     100     000     DS:[EAX+(scale*index)+disp8]
     01     100     001     DS:[ECX+(scale*index)+disp8]
     01     100     010     DS:[EDX+(scale*index)+disp8]
     01     100     011     DS:[EBX+(scale*index)+disp8]
     01     100     100     SS:[ESP+(scale*index)+disp8]
     01     100     101     SS:[EBP+(scale*index)+disp8]
     01     100     110     DS:[ESI+(scale*index)+disp8]
     01     100     111     DS:[EDI+(scale*index)+disp8]
 
     10     100     000     DS:[EAX+(scale*index)+disp32]
     10     100     001     DS:[ECX+(scale*index)+disp32]
     10     100     010     DS:[EDX+(scale*index)+disp32]
     10     100     011     DS:[EBX+(scale*index)+disp32]
     10     100     100     SS:[ESP+(scale*index)+disp32]
     10     100     101     SS:[EBP+(scale*index)+disp32]
     10     100     110     DS:[ESI+(scale*index)+disp32]
     10     100     111     DS:[EDI+(scale*index)+disp32]
 
     The operand [EBP] must be encoded as [EBP+0]; the 0 is an 8-bit
     displacement. Similarly, [EBP+(scale*index)] must be encoded as
     [EBP+(scale*index)+0]. The short encoding form available with
     other base registers cannot be used with EBP.
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