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     Instruction timings are calculated using these symbols:
 
     Symbol      Description
 
     EA          Effective address calculation time.
                 See: ►EA Calculation◄
 
     b,w,d,q     Byte, word, doubleword, or quadword integer operands.
 
     s,l,t       Short real, long real, and 10-byte temporary real
                 operands.
 
     pm          Timing for protected mode.
 
     n           Number of iterations. Repeated instructions may have a
                 base number of clocks plus a number of clocks for each
                 iteration. For example, 8+4n means eight clocks plus
                 four clocks for each iteration.
 
     noj         No jump. Timing of instruction if conditional jump not
                 taken.
 
     m           Next instruction components. Some control transfer
                 instructions take different times depending on the
                 length of the next instruction executed. On the 8088
                 and 8086, m is never a factor. On the 80286, m is the
                 number of bytes in the next instruction. On the 80386,
                 m is the number of components in the next instruction.
                 A component is an instruction byte or a displacement
                 or data operand.
 
     to,fr       To or from stack top. On the 80387, the to clocks
                 represent timings when ST is the destination. The fr
                 clocks represent timings when ST is the source.
 
     88          Timing for an 8088 processor.
 
     W88         Timing for an 8088 processor when operand is a word.
 
     On the 80286-80486 processors, add one clock cycle if a base,
     an index, and displacement are all used by the instruction.
 
     Convert clocks to nanoseconds by dividing one microsecond by the
     number of megahertz (MHz) at which the processor is running. For
     example, on a processor running at 8 MHz, one clock takes 125
     nanoseconds (1000 MHz per nanosecond/8 MHz).
 
     The clock counts are for best-case timings. Actual timings vary
     depending on wait states, alignment of the instruction, status of
     the prefetch queue, and other factors.
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